QuietEdge Public Technical Brief
This brief provides a non-confidential engineering overview of the QuietEdge power architecture, control philosophy, validation approach, and commercial integration model. It is intended for engineers, technical evaluators, and potential OEM partners who want to understand what QuietEdge is building before requesting confidential materials.
Architecture overview
Observer-first, bounded-influence control
The QuietEdge architecture is built around a core principle: the converter observes before it acts. An observer layer builds a model of system state — voltage, current, operating regime, transition conditions — before any bounded influence is introduced. Hardware protection remains independent and cannot be bypassed by the observer layer.
Observer layer
State observation before action
The converter enters hardware as an observer. It characterizes the baseline operating state before any control influence is introduced. This ensures that any subsequent A/B comparison has a clean, documented baseline.
Bounded influence
Safety-gated supervisory override
Control influence is introduced within a bounded envelope. The supervisory layer can adjust strategy; the converter executes within defined safety limits. Hardware protection operates independently and cannot be overridden.
Fast local response
Microsecond-to-millisecond timescale
Local control logic handles events that occur on timescales too fast for centralized management: load transients, fault conditions, inter-converter interactions on a shared DC bus.
Adaptive observation
Observation density matched to system state
Observation intervals adapt to information content: dense during transitions, relaxed during stable regimes. This reduces computational overhead without reducing observation quality where it matters.
Validation approach
Baseline-first, observer-first validation
QuietEdge validation follows a staged approach: establish a documented baseline, then introduce bounded influence and compare. Every result is labeled with its evidence class.
Control-code execution timing — TI AM2634
Measured execution time: 4.07 µs average / 4.69 µs maximum, with approximately 59% average timing headroom against a 10 µs loop budget.
This is embedded control-code timing, not full power-system response.
Reference-model A/B results
In paired QuietEdge reference-model A/B runs: recovery after peak ~216 ms → ~72 ms; peak ripple 47.91 mV → 41.42 mV; dither-energy proxy 3,848 → 596 deg²·ms.
Simulation / reference-model results. Not bench results, SST performance, or production performance.
800 V-class SiC DAB hardware validation
Staged 800 V-class SiC dual-active-bridge hardware validation is underway. Results will be published when available.
What QuietEdge does not claim
- Deployed or production-validated power systems
- Certified OCP or other standards compliance
- Customer deployments or field installations
- Exact algorithm weights, thresholds, or optimized mapping curves (not published publicly)
Integration model
How QuietEdge IP integrates into OEM platforms
QuietEdge is not a converter manufacturer. The IP is designed to integrate into existing OEM converter platforms. The integration model is flexible and can be adapted to the OEM's existing architecture and development process.
Algorithm licensing
License control algorithms for integration into the OEM's existing firmware and control architecture.
Reference architecture
Adopt QuietEdge reference DC power architectures for new platform development or system integration.
Co-development
Joint development program to adapt and validate QuietEdge IP for a specific converter platform and application.
Related QuietEdge pages